1. Field of the Invention
The present invention relates to integrated circuit fabrication and more particularly to the formation of metal layers used in integrated circuits.
2. Description of the Background Art
In the fabrication of integrated circuits (IC's), substrate surface planarity is of critical importance. This is especially so as the scale of integration increases and device features are reduced in size (e.g., sub-micron sizes). Integrated circuits typically include metal layers that are used to interconnect individual devices of the IC. The metal layers are typically isolated from each other by one or more dielectric material layers. Features (e.g., trenches, vias, etc.) formed through the dielectric layers provide electrical access between successive conductive interconnection layers.
Copper is becoming a metal of choice in integrated circuits for the metal layers that provide the electrical access between successive interconnection layers. Copper is a material having advantageous properties such as lower resistance and better electromigration performance compared to traditional materials such as aluminum.
Copper may be deposited by various techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD) and electrochemical plating (ECP). ECP is seen as a low cost and effective deposition technique with promise. ECP entails the deposition of a metal conductive layer on a substrate by contacting the substrate with an electrolyte solution and providing an electrochemical potential between two electrodes. Copper ions plate out of the electrolyte solution and deposit onto the substrate.
However, copper is difficult to pattern and etch. Accordingly, copper features are typically formed using damascene or dual damascene processes. In damascene processes, a feature is defined in a dielectric material and subsequently filled with copper. The copper is deposited both in the features and on the surrounding field. The copper deposited on the field is then removed to leave the copper filled feature formed in the dielectric.
The copper deposited on the field may be removed using techniques such as chemical mechanical polishing (CMP). CMP is a common technique used to planarize substrates. In CMP, a chemical polishing slurry, or other fluid medium, used in conjunction with mechanical energy removes material from the substrate surface. In order to obtain a flat surface topography for the copper filled features using a CMP process, a thick layer of copper (e.g., thicknesses about 2 times that of the dielectric material) is typically deposited on the substrate and then removed during a subsequent CMP process. Depositing a thick copper layer and then removing it, undesirably wastes copper increasing fabrication costs as well as decreasing integrated circuit throughput.
Therefore, a need exists in the art for an improved method for depositing and planarizing a metal layer, such as a copper layer, on a substrate.